High Speed Architecture Design Of Viterbi Decoder Using Verilog HDL
نویسندگان
چکیده
The main purpose of this study is to yield the gains obtained by the developers with the usage of Viterbi algorithm. Research mainly centers on the grandness of Viterbi algorithm in the practical applications with the VHDL code. Research not only helps the students related to the communications but it also helps the people who are in the field of decoders as it is one of the efficient method for reducing the errors while communication procedure is in advance. Here, VHDL code is used in order to implement the Viterbi algorithm in a proper way. Apart from various codes, researcher selected VHDL code for this research as it offers the high capability in designing the electronic systems. Students and the business people and one can easily understand and analyze the Viterbi algorithm concepts and can gain more knowledge on the VHDL code and the tools that are used in this research.
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